1. Field of the Invention
The invention relates to a clock reproducing device and a clock reproducing method for reproducing a clock of a transmitting side using clock information transmitted from the transmitting side at a receiving side in a communication apparatus or a broadcasting apparatus.
2. Description of the Prior Art
FIG. 11 is a block diagram showing a conventional clock reproducing device disclosed, for example, on the Recommendation H.222. 0, pages 182-184 in ITU-T White Book, of Japanese version, which correspond to "pages 126-128 of English version" A Collection book of Recommendation on Audio Visual/Multimedia (H series), published on Feb. 18, 1995 by an incorporated foundation, Japan ITU Association. In FIG. 11, the clock reproducing device includes a voltage-controlled oscillator 11, a counter 12 operating by a reproduced clock outputted from the voltage-controlled oscillator 11, a clock difference detector 13, and a low-pass filter/gain device 14.
In the above mentioned Recommendation, the clock information transmitted from the transmitting side is referred to as a PCR (program clock reference), and the clock information reproduced on the receiving side is referred to as an STC (system time clock). The PCR is a count value of a counter operating by the clock used on the transmitting side. On the other hand, the STC is a count value 12 operating by the clock reproduced on the receiving side.
FIG. 11 also shows a difference 15 between the PCR and the STC calculated by the clock difference detector 13, a control voltage 16 outputted from the low-pass filter/gain device 14 to the voltage-controlled oscillator 11.
Usually, the receiving side's free-running system clock frequency will not match the transmitting side's clock frequency which is sampled and indicated in the SCR values. The receiving side's STC can be made to slave its timing to the transmitting side using the received SRCs. The conventional method of slaving the receiving side's clock to the received data stream is via a phase-locked loop (PLL). Variations of a basic PLL, or other methods, may be appropriate, depending on the specific application requirements. A straightforward PLL which recovers the STC on the receiving side is diagrammed and described in FIG. 11. FIG. 11 shows a classic PLL, except that the reference and feedback terms are numbers (STC and SCR or PCR values) instead of signal events such as edges.
Upon initial acquisition of a new time base, i.e., a new program, the STC is set to the current value encoded in the SCRs. Typically, the first SCR is loaded directly into the STC counter, and the PLL is subsequently operated as a closed loop. Variations on this method may be appropriate, i.e., if the values of the SCRs are suspect due to jitter or errors.
The closed loop action of the PLL is as follows. At the moment that each SCR (or PCR) arrives at the receiving side, that value is compared with the current value of the STC in the clock difference detector 13. The difference 15 is a number, which has one part in units of 90 kHz and one part in terms of 300 times this frequency, i.e., 27 MHz. The difference 15 is linearized to be in a single number space, typically units of 27 MHz, and is the error term in the loop. The sequence of error terms (which make up difference 15) is input to the low-pass filter and gain device 14, which are designed according to the requirements of the application. The output of device 14 is the control voltage 16 which controls the instantaneous frequency of the voltage controlled oscillator (VCO) 11. The output of the VCO 11 is an oscillator signal with a nominal frequency of 27 MHz; this signal is used as the system clock frequency on the receiving side. The 27 MHz clock is input to counter 12 which produces the current STC values, which consist of both a 27 MHz extension, produced by dividing by 300, and a 90 kHz base value which is derived by counting the 90 kHz results in a 33 bit counter. The 33 bit, 90 kHz portion of the STC output is used as needed for comparison with PTS and DTS values. The complete STC is also the feedback input 101 to the clock difference detector 13.
Next, an operation is explained below. In case of starting the reproduction of the transmitting clock at a receiver, the received transmitting clock information (PCR) 100 is first loaded in the counter 12. The counter 12 carries out counting using the reproduced clock outputted from the voltage-controlled oscillator 11.
When a second PCR 100 arrives, the reproduced clock information (STC) 101 which is an output of the counter 12 at this time is inputted into the clock difference detector 13, then, the difference 15 between the STC 101 and the secondly arrived PCR 100 is obtained.
Since the PCR 100 is a count value counted according to the clock of the transmitter and the STC is a count value counted according to the clock of the receiver, the difference between the PCR 100 and the STC 101 shows a value between a frequency of the clock of the transmitter and a frequency of the clock of the receiver.
In case that the clock frequency of the transmitter is higher than the clock frequency of the receiver by 20 Hz, an increase of a count value of the PCR 100 is larger than an increase of a count value of the STC 101 by 20 per second. On the other hand, if the difference 15 between the PCR 100 and the STC 101 becomes constant, it means that the frequencies of the transmitters and the receivers are the same.
If the difference 102 is constant every time the PCR 100 arrives, it means that increments of the both counters are the same, which also means the transmitting side frequency is the same as the reproduced frequency on the receiving side.
The difference 15 outputted from the clock difference detector 13 is converted to a control voltage by the low-pass filter/gain device 14, and outputted to the voltage-controlled oscillator 11. If the differential value is higher at a certain time, it increases the control voltage 16, and then the output frequency of the voltage-controlled oscillator 11 increases. Therefore, the output of the counter 12 increases, which causes the difference between the PCR 100 and the STC 101 to decrease gradually.
The above mentioned operation is repeated for every time when the PCR 100 arrives, and the frequency of the voltage-controlled oscillator 11 is controlled so that an output of the clock difference detector 13, i.e difference between the PCR 100 and the STC 101, is constant. In other words, the value counted up per a time on the reproducing side gradually becomes the same as that on the transmitting side, which means that the clock frequency on the reproducing side becomes the same clock frequency as on the transmitting side.
In a stable state in which the receiving side clock frequency is reproduced the same as that on the transmitting side, the difference between the PCR 100 and the STC 101 is generally kept to be a constant value (off-set). Though no off-set exists at first since the PCR 100 is loaded in the counter 12 at the beginning, the transmitting side frequency is different from the reproduced frequency because the transmitting side frequency is not reproduced yet at the receiving side. Then, the count value 12 gradually shifts away from the PCR 100 until the reproducing operation starts. But, after the reproducing operation starts, the reproduced frequency is controlled so that the difference is kept constant. Therefore, the off-set is kept even in the stable state.
As mentioned above, in the conventional clock reproducing device, the difference between the transmitting clock information (PCR) and the reproduced clock information (STC) is used as information which simply indicates a difference between the frequencies on the transmitting side and the receiving side. That is, the conventional clock reproducing device controls the reproduced frequency by the above difference value inputted into the low-pass filter/gain device 14. Therefore, the low-pass filter/gain device 14 is controlled by the inputted difference to output the constant control voltage if the difference is constant, regardless of the receiving interval of the transmitting clock information.
The difference between the transmitting clock information and the reproduced clock information is proportional to the receiving interval of the transmitting clock information. Therefore, even if the frequency difference is constant, the outputted difference can be different depending on the length of the transmitting intervals of the transmitting clock information. Accordingly, even if the length of the transmitting intervals of the transmitting clock information is different, it is necessary to output the constant control voltage to the oscillator to decrease the constant frequency difference. Therefore, the same low-pass filter/gain device 14 can not be used if the transmitting intervals of the transmitting clock information is different. Accordingly, it is necessary to take proper steps according to the transmitting intervals of the transmitting clock information.
Furthermore, in case that the voltage-controlled oscillator is used, a practical relation of the output frequency versus the control voltage often differs from that shown in a catalog. Consequently, it is necessary to adjust the above relation of the output frequency versus the control voltage by measuring the actual characteristics of the control voltage and the output frequency of the voltage-controlled oscillator every time a system is constructed.
In the conventional clock reproducing device, the difference is controlled to be constant since the constant difference between the transmitting clock information and the reproduced clock information means that the frequency of transmission clock is the same as that of reception clock. Still, the difference between the PCR and the STC includes the off-set as mentioned above. Therefore, in a receiver which processes the data by synchronizing the value of the transmitting clock information with the value of the reproduced clock information, if the difference between the received transmitting clock information and the reproduced clock information is large, it is necessary to store the data for the time corresponding to the difference into the receiver, which requires a buffer large enough to absorb the difference. Consequently, it is necessary to design according to the quantity of the differential value, and therefore the cost increases because of an increase of hardware such as the buffer. Furthermore, the count value becomes discontinuous when the count value is loaded or reset after the start of the reception procession, which disturbs the operation of the data processing apparatus.
It is an object of the present invention to solve the above mentioned problems, and to provide a clock reproducing device and a clock reproducing method appropriately controlled regardless of the transmitting interval of the transmitting clock information. Where, the "transmitting interval" means an interval in which a clock information is outputted at the transmitting side. On the other hand, a "receiving interval" of the transmitting clock information means an interval in which a clock information is received at the receiving side. In general, the "transmitting interval" of the transmitting clock information and the "receiving interval" of the transmitting clock information are substantially the same. However, in some cases, they are different if the transmitting clock and the receiving clock are different.
It is another object of the present invention to provide a clock reproducing device and the clock reproducing method which are not necessary to be adjusted according to the dispersion of the characteristic of the control voltage and the dispersion of the output frequency of the oscillator.
It is further object of the present invention to provide a clock reproducing device and the clock reproducing method in which the receiver design is facilitated by minimizing the difference between the received transmitting clock information and the reproduced clock information.